The StarTech Massively Parallel Chess Program Bradley C. Kuszmaul http://theory.lcs.mit.edu/Äbradley Laboratory for Computer Science Massachusetts Institute of Technology

Source URL: www.top-5000.nl

Massively-Parallel Heterogeneous Computing for Solving Large Problems Wen-mei Hwu, Mert Hidayeto˘glu, Carl Pearson, Simon Garcia, Sitao Huang, and Abdul Dakkak Coordinated Science Laboratory, University of Illinois at U

Source URL: impact.crhc.illinois.edu

Massively-Parallel Heterogeneous Computing for Solving Large Problems Wen-mei Hwu Professor and Sanders-AMD Chair, ECE, NCSA University of Illinois at Urbana-Champaign

Source URL: impact.crhc.illinois.edu

Transactions on Parallel and Distributed Systems Dynamic Resource Provisioning in Massively Multiplayer Online Games rP

Source URL: www.st.ewi.tudelft.nl

Scalable Compression and Replay of Communication Traces in Massively Parallel Environments ∗ Michael Noeth1 , Frank Mueller1 , Martin Schulz2 , Bronis R. de Supinski2 1

Source URL: moss.csc.ncsu.edu

Scalable Unix Tools on Massively Parallel Processors William Gropp and Ewing Lusk ∗ January 4, 1995

Source URL: wgropp.cs.illinois.edu

Massively Parallel Methods for Deep Reinforcement Learning arXiv:1507.04296v2 [cs.LG] 16 Jul 2015 Arun Nair, Praveen Srinivasan, Sam Blackwell, Cagdas Alcicek, Rory Fearon, Alessandro De Maria, Vedavyas Panneershelvam,

Source URL: arxiv.org

Query Optimization for Massively Parallel Data Processing Sai Wu #1 , Feng Li #2 , Sharad Mehrotra §3 , Beng Chin Ooi #4 # School of Computing, National University of Singapore, Singapore, ,2,4

Source URL: www.comp.nus.edu.sg

® Kalray MPPA Massively Parallel Processor Array Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor Benoît Dupont de Dinechin, CTO

Source URL: www.hotchips.org

• Computing
• Parallel computing
• Computer architecture
• Manycore processors
• Digital signal processing
• Microprocessors
• Massively parallel processor array
• Multi-core processor
• Xeon Phi
• Massively parallel
• Digital signal processor
• Very long instruction word

Transactor-based debugging of massively parallel processor array architectures Markus Blocherer, Srinivas Boppu, Vahid Lari, Frank Hannig, Jürgen Teich Hardware/Software Co-Design University of Erlangen-Nuremberg

Source URL: www.mad-workshop.de

• Computing
• Computer architecture
• Electronic engineering
• VHDL
• ModelSim
• Field-programmable gate array
• ARC
• Synopsys
• Router